XCVU13P-2FLGA2577E

XCVU13P-2FLGA2577E

​XCVU13P-2FLGA2577E Virtex™ UltraScale+ ™ The device provides the highest performance and integrated functionality on the 14nm/16nm FinFET node. AMD's third-generation 3D IC uses stacked silicon interconnect (SSI) technology to break the limitations of Moore's Law and achieve the highest signal processing and serial I/O bandwidth to meet the strictest design requirements

Model:XCVU13P-2FLGA2577E

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Product Description

XCVU13P-2FLGA2577E Virtex™ UltraScale+ ™  The device provides the highest performance and integrated functionality on the 14nm/16nm FinFET node. AMD's third-generation 3D IC uses stacked silicon interconnect (SSI) technology to break the limitations of Moore's Law and achieve the highest signal processing and serial I/O bandwidth to meet the strictest design requirements. It also provides a virtual single-chip design environment to provide registered routing lines between chips, enabling operation above 600MHz and offering richer and more flexible clocks.




As the most powerful FPGA series in the industry, UltraScale+devices are the perfect choice for computationally intensive applications, ranging from 1+Tb/s networks, machine learning to radar/warning systems.




application


Calculation acceleration


5G baseband


wire communication


radar


Testing and Measurement




Main features and advantages


3D-on-3D integration:


-FinFET supporting 3D IC is suitable for breakthrough density, bandwidth, and large-scale die to die connections, and supports virtual single-chip design


Integrated blocks of PCI Express:


-Gen3 x16 integrated PCIe for 100G applications ®  modular


Enhanced DSP Core:


-Up to 38 TOPs (22 TeraMAC) of DSP have been optimized for fixed floating point calculations, including INT8, to fully meet the needs of AI inference


Memory:


-DDR4 supports on-chip memory cache speeds of up to 2666Mb/s and up to 500Mb, providing higher efficiency and low latency


32.75Gb/s transceiver:


-Up to 128 transceivers on the device - backplane, chip to optical device, chip to chip functionality


ASIC level network IP:


-150G Interlaken, 100G Ethernet MAC core, capable of high-speed connection


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